`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:18:13 03/05/2013
// Design Name:
// Module Name: sig_hys
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
	module sig_hys(
	input dir_sig,
	input clk,
	input reset_b,
	output fil_sig
	);
	
	
	reg temp_reg_i; // One clock shifted signal
	
	
		parameter TURN_ON_CLOCK_COUNT = 6;
		parameter TURN_OFF_CLOCK_COUNT = 4;
		reg [3:0]ON_COUNT = 0;
		reg [3:0]OFF_COUNT = 0;
		
always @ (posedge clk or negedge reset_b)
	begin
	if(reset_b == 1'b0) begin
		temp_reg_i <= 1'b0;
		end
	
	else if(dir_sig == 1'b1)
			 begin
				if(ON_COUNT == TURN_ON_CLOCK_COUNT)
					begin
						temp_reg_i <=1'b1;
					end
				else
					begin
						ON_COUNT = ON_COUNT+1;
						OFF_COUNT =0;
						$display("OnCount = %d", ON_COUNT );
					end
			 end

	else if(dir_sig == 1'b0)
		begin
			if(OFF_COUNT==TURN_OFF_CLOCK_COUNT)
				begin
					temp_reg_i <= 1'b0;
				end
			else
				begin
					OFF_COUNT = OFF_COUNT+1;
					ON_COUNT = 0;
					$display("OffCount = %d", OFF_COUNT);
				end

		end
end
assign fil_sig = temp_reg_i;

endmodule

